The wafer is functional; the economics remain open
Infineon said on November 9 that it had processed 300-millimeter silicon carbide (SiC) wafers into functional power devices at its Villach fab, using existing silicon manufacturing equipment. The company says the larger wafer offers 2.3 times more chips per wafer than a 200-millimeter wafer. It also calls this an early achievement: the technology and ramp timing will be planned with customers and partners, while the company continues its 200-millimeter SiC roadmap S1.
That timing distinction is the story. Semiconductor Today likewise describes the result as demonstrating the potential for future industrialization, not as a high-volume production ramp S2. The announcement gives no yield figures, cost per die, qualified production volume or ramp date. So the 2.3-times figure is a chip-count claim at wafer level—not evidence of 2.3-times output, or a matching reduction in device cost.
A larger wafer can improve the economics only if the extra usable die survive the process at competitive yield and throughput. Device layout, wafer-edge losses, defects and downstream test and packaging all affect sellable parts. That is the practical gap between showing functional devices on a larger substrate and proving a cheaper, dependable supply stream.
What engineers should ask next
Infineon also says it demonstrated the feasibility of its Cold Split process with 300-millimeter SiC in Dresden. The technique separates wafers from a SiC boule with less material loss and shorter processing time than conventional wire sawing, potentially improving how much wafer material can be recovered S1. That addresses an upstream materials step; it does not by itself establish yield or throughput for the complete device process.
For power-electronics teams, the potential applications include traction inverters, EV chargers, energy storage and industrial drives, areas Infineon names in its announcement S1. But designers and buyers should not revise a bill of materials or qualification plan on wafer diameter alone. Ask when a specific device and package will be production-qualified, what volume can be delivered, and whether cost and supply advantages hold at the target yield. Until those answers exist, treat 300-millimeter SiC as a manufacturing milestone—not a procurement assumption. The meaningful proof will be qualified devices arriving at the promised cost and volume, not a larger wafer on display.
Sources and editorial method
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Common questions
Does Infineon’s 300mm SiC milestone mean lower device prices now?
No. Infineon reported functional devices on 300mm wafers, but did not disclose production yields, costs or a ramp date.
What should hardware teams verify before redesigning around 300mm SiC?
Confirm the qualified device and package, delivery schedule, available volume, and cost at the intended production yield.


