Zen 6 Splits the Server Core in Two

When AMD announced in May that its "Venice" EPYC generation had begun ramping on TSMC's 2nm process — the first HPC product to reach production on that node S2 — the process node was never the interesting part; the question was what AMD changed inside the cores. Today Chips and Cheese published microarchitectural measurements of Zen 6 server silicon, and the answer is bigger than a generational bump: classic Zen 6 and dense Zen 6c are no longer the same core at two densities. They are two different cores, each shaped for where it will run S1.

One ISA, two out-of-order engines

In past generations, AMD's "c" dense variants were functionally identical to the classic cores, differing mainly in cores per CCD and L3 per core. Zen 6 moves the fork inside the pipeline. Zen 6c carries a 640-entry reorder buffer against 576 on Zen 6, a 352-entry integer register file against 288, 180 vector scheduler entries against 138, and a 330-entry load queue against 280 S1. The cache hierarchy mirrors the split: Zen 6 gets 12-core CCDs with 48 MB of L3; Zen 6c gets 32-core CCDs with 128 MB. In plain terms, Zen 6 is tuned for clocks, while Zen 6c trades frequency for the capacity to absorb memory latency.

What the measurements actually say

Three results stand out for planners. First, L3 latency grew in cycles — from about 47 on Zen 5 to 55 on Zen 6 and 66 on Zen 6c — but in nanoseconds the classic part barely moves: 10.7 ns versus 10.3 ns on Zen 5, while Zen 6c pays 16.4 ns S1. Second, the estimated SPEC CPU 2026 results put the high-clock EPYC 9686F roughly 21 percent ahead of the Zen 5-based EPYC 9575F in integer and 18 percent in floating point, while the 256-core EPYC 9996 (1 GB of L3, up to 4.1 GHz boost on AMD's spec sheet S4) roughly matches that same Zen 5 part in single-threaded performance at about 900 MHz lower clocks — and, in Chips and Cheese's numbers, edges NVIDIA's Vera in integer while leading it by about 20 percent in floating point. Third, memory-heavy workloads stall hard on the fast part: at matched clocks, backend memory stalls in 765.roms reach 50.3 percent of pipeline slots on the 9686F versus 42.5 percent on the 9996, and big-codebase tests show far heavier frontend stalls on the classic part S1.

There is a quiet inference story too: VNNI throughput doubles to roughly 3.88 instructions per cycle on 512-bit operations, and 256-bit vector loads double to four per cycle — relevant because most deployed vector code still targets AVX1/2 S1.

Placement is now a design decision

The practical takeaways:

• Stop treating classic and dense SKUs as the same product with a socket discount. Scheduler placement now matters: memory-bound jobs belong on Zen 6c's bigger buffers and 128 MB of L3; latency-sensitive services on classic cores.
• Vendor benchmarks and independent measurements tell complementary stories. NVIDIA positions Vera as one CPU spanning both ends, claiming 1.6x more agents per watt than the fastest x86 CPU and twice the agent speed of its most energy-efficient part in a 100-megawatt comparison S3. Chips and Cheese's independent runs show AMD's dense flagship competitive or ahead in both suites S1. Read both before standardizing.
• The CPU layer is now AI-factory plumbing. AMD frames the server CPU as coordinator of data movement, networking, storage and orchestration as agentic workloads scale S2.

The spec sheet used to settle CPU purchases. With two out-of-order engines under one ISA, workload telemetry does.